Flash memory device and fabrication method thereof

ABSTRACT

A flash memory device and fabrication method simplify the fabrication process of a semiconductor EEPROM device through a self-aligning process. The device includes a semiconductor substrate in which source and drain regions are defined, a first insulation layer formed on the semiconductor substrate, a first conductive layer pattern formed on a portion of the first insulation layer, sidewall spacers formed of a second conductive layer neighboring each sidewall of the first conductive layer pattern and covered by second and third insulation layers, and a third conductive layer pattern formed on the insulation layers and connected with the first conductive layer pattern.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to memory devices and, inparticular, to a flash memory device and a fabrication method thereof

[0003] 2. Background of the Related Art

[0004]FIG. 1 illustrates a related art Floating-gate Tunneling Oxide(FLOTOX Electrically Erasable and Programmable Read Only Memory(EEPROM). An active region 1 a and a field region 1 b are formed on theupper surface of a semiconductor substrate 1. In the semiconductorsubstrate 1, source and drain regions 2 and 3 are formed. A gateinsulation layer 4 and a tunnel insulation layer 5 are formed within theactive region 1 a of the semiconductor substrate 1. A first conductivelayer (floating gate) 6 is formed on the upper surfaces of the gateinsulation layer 4 and the tunnel insulation layer 5. An interlayerinsulation film 7 is formed on the upper surface of the first conductivelayer 6. A second conductive layer (control gate) 8 is formed on theupper surface of the interlayer insulation film 7. An insulation film 9is formed on the upper surfaces of the semiconductor substrate 1 and thesecond conductive layer 8.

[0005] In operation, twenty volts (20V) is supplied to the control gate8 and zero volts (0V) is supplied to the drain 3. The source 2 and thesubstrate 1 are connected to ground. Electrons are injected into thefloating gate 6 from the drain 3 through the tunnel insulation layer 5via a Folwer-Nordheim (FN) tunneling effect. Electrons accumulate in thefloating gate 6, the threshold voltage of the device increases, and theintensity of the electric field, which is applied from the control gate8 to the drain 3, increases.

[0006] To erase the data from the FLOTOX EEPROM, the source 2 and thesemiconductor substrate 1 are connected to ground, zero volts issupplied to the control gate 8 and twenty volts are supplied to thedrain 3. Electrons accumulated in the floating gate 6 are moved into thedrain region 3 through the tunnel insulation layer 5 via the FNtunneling effect. Since the number of electrons in the floating gate 6decrease, the threshold voltage of the FLOTOX EEPROM decreases, and theintensity of the electric field, which is applied from the drain 3 tothe control gate 8, also decreases.

[0007] The related art FLOTOX EEPROM requires a high voltage duringprogramming and data erasing operations, and a high substrate current isgenerated due to the high voltage during data erasing operations. As aresult, the characteristics of the FLOTOX EEPROM and the tunnelinsulation layer 5 are quickly degraded.

[0008] In addition, due to the high substrate current generated, it isnot possible to erase the data in the related art FLOTOX EEPROM using a5-volt power source. Furthermore, it is not possible to perform aself-aligning process during the fabrication process for the related artFLOTOX EEPROM.

[0009] The above references are incorporated by reference herein whereappropriate for appropriate teachings of additional or alternativedetails, features and/or technical background.

SUMMARY OF THE INVENTION

[0010] Accordingly, it is an object of the present invention to providea flash memory device and a flash memory fabrication method thatovercome the aforementioned problems encountered in the related art.

[0011] It is another object of the present invention to perform a dataerasure at a low voltage.

[0012] It is another object of the present invention to simplify thefabrication process of the memory device through a self-aligningprocess.

[0013] To achieve the above objects, there is provided a flash memorydevice comprising: (1) a semiconductor substrate; (2) a source regionand a drain region in the semiconductor substrate; (3) a firstinsulation layer formed on the semiconductor substrate; (4) a firstconductive layer formed on a portion of the first insulation layer; (5)first and second conductive sidewall spacers positioned adjacent tofirst and second sidewalls of the first conductive layer, respectively;(6) a second insulation layer formed on the first and second sidewallconductive sidewall spacers; and (7) a second conductive layer formed onthe insulation layer, the second conductive layer in electrical contactwith the first conductive layer.

[0014] To achieve the above objects, there is also provided a flashmemory device fabrication method, which comprises the steps of: (1)forming a first insulation layer on a semiconductor substrate; (2)forming a first conductive layer pattern on a portion of the firstinsulation layer; (3) forming low density impurity regions in thesemiconductor substrate; (4) forming a second insulation layer onsidewalls of the first conductive layer pattern; (5) forming, on each ofthe sides of the first conductive layer pattern, a conductive sidewallspacer on the second insulation layer and the first insulation layer;(6) forming high density impurity regions in the semiconductorsubstrate; (7) forming a third insulation layer that covers theconductive sidewall spacers and that contacts the first and secondinsulation layers; and (8) forming a third conductive layer pattern onthe first, second and third insulation layers, the third conductivelayer pattern in electrical contact with the first conductive layerpattern.

[0015] Additional advantages, objects, and features of the inventionwill be set forth in part in the description which follows and in partwill become apparent to those having ordinary skill in the art uponexamination of the following or may be learned from practice of theinvention. The objects and advantages of the invention may be realizedand attained as particularly pointed out in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The invention will be described in detail with reference to thefollowing drawings in which like reference numerals refer to likeelements wherein:

[0017]FIG. 1 is a horizontal cross-sectional view of related artfloating-gate tunneling oxide (FLOTOX) EEPROM;

[0018]FIG. 2 is a horizontal cross-sectional view of a flash memorydevice according to the present invention;

[0019]FIG. 3 is a plan view of the flash memory device of FIG. 2; and

[0020]FIGS. 4A-4C are cross-sectional views illustrating process stepsof a preferred method for fabricating a flash memory device according tothe present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0021]FIGS. 2 and 3 illustrate a flash memory device according to thepresent invention. As shown therein, the flash memory device accordingto the present invention comprises a semiconductor substrate 11 havingan active region 11 a and field regions 11 b formed thereon, and sourceand drain regions 12 and 13, respectively, defined in the semiconductorsubstrate 11. The source region 12 and the drain region 13 include lowdensity doping regions 12 a and 13 a, respectively, and high densitydoping regions 12 b and 13 b, respectively. In addition, a firstinsulation layer 14 is formed on the active region 11 a of thesemiconductor substrate 11. The first insulation layer 14 includes agate insulation layer 14 a, and a tunnel insulation layer 14 b formed onthe upper surfaces of the source and drain regions 12 and 13.

[0022] A first conductive layer (first control gate) 15 is formed on theupper surface of the gate insulation layer 14 a. Second conductive layersidewall spacer (floating gate) 18 are formed on each sidewall of thefirst control gate 15, and are covered by a second insulation layer(sidewall insulation layer) 16 and a third insulation layer (sidewallinsulation layer) 17. In addition, a third conductive layer pattern(second control gate) 19 is formed on the upper surfaces of theinsulation layers 14, 16 and 17, and is connected with the first controlgate 15.

[0023] As shown in FIG. 4A, an active region 11 a and a field region 1lb are defined on the upper surface of the semiconductor substrate 11,e.g., a P-type substrate, preferably by a LOCOS process. A firstinsulation layer (not shown) is deposited on the semiconductor substrate11, preferably by a CVD method, and a predetermined portion of theactive region 11 a is patterned in order to form a gate insulation layer14 a. On the remaining portions of the active region 11 a, a tunnelinsulation layer 14 b is formed thinner than the thickness of the gateinsulation layer 14 a. A first conductive layer (not shown) is depositedon the upper surface of the semiconductor substrate 11 including thegate insulation layer 14 a, preferably by a CVD method, and theresultant structure is patterned. The first conductive pattern (firstcontrol gate) 15 is then formed on the upper surface of the gateinsulation layer 14 a.

[0024] Thereafter, low density impurity regions (source/drain regions)12 a and 13 a are formed, preferably by ion-implanting impurities intothe semiconductor substrate 11 using the gate insulation layer 14a andthe first control gate 15 as a mask. A nitride film (not shown) isdeposited on the semiconductor substrate 11, including the first controlgate 15 and the resultant structure is patterned. The nitride filmpattern 20 is then formed by leaving the nitride film (not shown) ononly the upper surface of the first control gate 15.

[0025] Referring to FIG. 4B, a second insulation layer (not shown) and asecond conductive layer (not shown) are sequentially formed on the uppersurface of the structure of FIG. 4A, including the nitride film pattern20, preferably by a CVD process. The second insulation layer and thesecond conductive layer are then dry-etched, and a sidewall insulationlayer 16 and second conductive layer sidewall spacer (floating gate) 18are formed by forming the second insulation layer (sidewall insulationlayer) (not shown) and the second conductive layer (not shown) on thesidewall surfaces of the first control gate 15 and the nitride filmpattern 20. Next, the upper surface of the nitride film pattern 20 isexternally exposed. A high density of impurities are then ion-implantedinto the semiconductor substrate 11 by using the nitride film pattern 20and the floating gate 18 as a mask, thereby defining the source anddrain regions 12 and 13, respectively, having high density impurityregions neighboring with the low density impurity regions.

[0026] Referring to FIG. 4C, the nitride film pattern 20 is etched, anda third insulation layer 17 is deposited on the upper surfaces of thefirst control gate 15, the floating gate 18, the first insulation layer14, and the second insulation layer 16. Then, the portion of the thirdinsulation layer 17 formed on the upper surface of the first controlgate 15 is etched by using an etching mask. Thereafter, a thirdconductive layer (not shown) is deposited on the upper surfaces of thefirst control gate 15 and third insulation layer (sidewall insulationlayer) 17, preferably by a CVD process. The resultant structure is thenpatterned and connected with the first control gate 15, thereby forminga third conductive layer pattern (second control gate) 19. Thiscompletes the fabrication of the flash memory device structure accordingto the present invention.

[0027] To program the flash memory device, a positive low voltage isfirst supplied to the second control gate 19, a negative low voltage isapplied to the source and drain regions 12 and 13, and the semiconductorsubstrate 11 is grounded. Based on the electrical field formed betweenthe second control gate 19 and the source and drain 12 and 13, electronsfrom the source and drain regions 12 and 13 are injected into eachfloating gate 18 through the tunnel insulation layer 14 b via the FNtunneling effect. When electrons have accumulated in the floating gate18, the threshold voltage of the flash memory device is increased, andthe intensity of the electric field is increased.

[0028] During the data erasure operation, a negative low voltage issupplied to the second control gate 19, a positive low voltage issupplied to the source and drain regions 12 and 13, and thesemiconductor substrate 11 is connected to ground. Based on theelectrical field formed between the source and drain regions 12 and 13,and the second control gate 19, electrons accumulated in the floatinggate 18 are injected into the source and drain regions 12 and 13 throughthe tunnel insulation layer 14 b via the FN tunneling effect. As aresult, the number of electrons from the floating gate 18 is reduced,the threshold voltage of the flash memory device is decreased, and theintensity of the electric field is decreased.

[0029] As described above, the flash memory device and fabricationmethod according to the present invention provide a flash memory whichis capable of rapidly performing data erasure and programming operationsat low voltage by forming a floating gate on both sidewalls of thecontrol gate and on the low density impurity regions (source and drain),simplifying the fabrication process by using a self-aligning process,and controlling the size of the floating gate.

[0030] The foregoing embodiments are merely exemplary and are not to beconstrued as limiting the present invention. The present teaching can bereadily applied to other types of apparatuses. The description of thepresent invention is intended to be illustrative, and not to limit thescope of the claims. Many alternatives, modifications, and variationswill be apparent to those skilled in the art.

What is claimed is:
 1. A memory device, comprising: a substrate; a firstregion and a second region in the substrate; a first insulation layerformed on the substrate; a first conductive layer formed on a portion ofthe first insulation layer; first and second conductive sidewall spacerspositioned adjacent to first and second sidewalls of the firstconductive layer, respectively; a second insulation layer formed on thefirst and second conductive sidewall spacers; and a second conductivelayer formed on the insulation layer, the second conductive layerconductively coupled to the first conductive layer.
 2. The device ofclaim 1 , wherein the first and second regions are source and drainregions, respectively, the source and drain regions each include a lowdensity doping region and a high density doping region.
 3. The device ofclaim 1 , wherein portions of the first insulation layer are formed overthe first and second regions.
 4. The device of claim 3 , wherein theportions of the first insulation layer formed over the first and secondregions are thinner than the portion of the first insulation layer onwhich the first conductive layer is formed.
 5. The device of claim 1 ,wherein the second insulation layer comprises portions that extendbetween the sidewall spacers and the first conductive layer.
 6. Thedevice of claim 1 , wherein the second insulation layer comprisesportions formed between the sidewall spacers and the third conductivelayer.
 7. The device of claim 1 , wherein portions of the secondinsulation layer project above an upper surface of the first conductivelayer pattern.
 8. The device of claim 1 , wherein the first and thirdconductive layers form control gates.
 9. The device of claim 1 , whereinthe first and second conductive sidewall spacers form a floating gate.10. The device of claim 1 , wherein the first and third conductivelayers and the first and second conductive layer sidewall spacers arepolysilicon.
 11. A method of making a memory device, comprising thesteps of: forming a first insulation layer on a substrate; forming afirst conductive layer pattern on a portion of the first insulationlayer; forming impurity regions in the substrate; forming a secondinsulation layer on sidewalls of the first conductive layer pattern;forming, on each of two sides of the first conductive layer pattern, aconductive sidewall spacer on the second insulation layer and the firstinsulation layer; forming a third insulation layer that covers theconductive sidewall spacers; and forming a third conductive layerpattern on the first, second and third insulation layers, the thirdconductive layer pattern conductively coupled to the first conductivelayer pattern.
 12. The method of claim 11 , wherein the third insulationlayer is formed so that it contacts the first and second insulationlayers.
 13. The method of claim 11 , wherein the step of formingimpurity regions in the substrate comprises the steps of: forming lowdensity impurity regions in the substrate; and forming high densityimpurity regions in the substrate.
 14. The method of claim 13 , whereinthe step of forming low density impurity regions comprises: forming anitride film pattern on the first conductive layer pattern;ion-implanting impurities in the substrate while using the nitride filmpatterns as a mask; and removing the nitride film pattern.
 15. Themethod of claim 13 , wherein the step of forming high density impurityregions comprises: forming a nitride film pattern on the firstconductive layer pattern; ion-implanting impurities in the substratewhile using the nitride film pattern and the conductive sidewall spacersas a mask; and removing the nitride film pattern.
 16. The method ofclaim 11 , wherein the first and third conductive layer patterns formcontrol gates.
 17. The method of claim 11 , wherein the conductivesidewall spacers form a floating gate.
 18. The method of claim 11 ,wherein the first and third conductive layer patterns and the conductivesidewall spacers are polysilicon.
 19. The method of claim 11 , whereinthe second insulation layer is formed between the conductive sidewallspacers and the first conductive layer pattern.
 20. The method of claim11 , wherein the third insulation layer is formed between the conductivelayer sidewall spacers and the third conductive layer pattern.
 21. Themethod of claim 11 , wherein portions of the second insulation layer andthe third insulation layer, which cover the conductive sidewall spacers,project above an upper surface of the first conductive layer pattern.22. The method of claim 13 , wherein a first low density impurity regionand a first high density impurity region together form a source region,and wherein a second low density impurity region and a second highdensity impurity region together form a drain region.
 23. The method ofclaim 22 , wherein portions of the first insulation layer are formedover the source and drain regions.
 24. The method of claim 23 , whereinthe portions of the first insulation layer formed over the source anddrain regions are thinner than the portion of the first insulation layeron which the first conductive layer is formed.